1. Field of the Invention
The present invention relates to a semiconductor device mounted on a board or the like having the function of carrying out a contact test at a relatively low cost to check a state of a contact of terminals of the semiconductor device, a method of testing the semiconductor device and a semiconductor integrated circuit.
In the process of mounting a semiconductor device consisting of a memory device such as a DRAM (dynamic random access memory) on a board or the like, it is important to confirm whether or not terminals of the memory device and terminals of the board are assuredly connected with each other by means of solder or the like, i.e., to carry out a contact check of the terminals of the memory device after the memory device is mounted on the board or the like.
Generally, a memory device such as a DRAM is packaged into a thin package of a surface mount type such as a TSOP (thin small outline package). The conditions of soldering of the terminals can be visually checked with these packages being mounted on the board, and therefore the contact check of the terminals of the memory device after the memory device is mounted on the board or the like, has thus far been carried out visually.
With a reduction of the size of a personal computer year by year, however, the packaging area of the memory device tends to decrease gradually. To meet the tendency toward the decrease in the packaging area of the memory device, in recent years a package having a smaller packaging area such as a CSP (chip size package) having substantially the same outer dimensions as a chip (1 cm square) has been fabricated. This type of package has a number of electrodes arranged in a matrix in the two-dimensional directions on the bottom thereof. Once the above type of package is mounted on the board, therefore, it is no longer easy to visually check the state of the contact of the terminals of the memory device.
2. Description of the Related Art
As described above, after packaging a memory device such as a DRAM into a package having a smaller packaging area (e.g., CSP) and mounting this particular package on a board, it is difficult to visually check the state of the contact of the terminals of the memory device. It is therefore necessary to carry out the contact check by actually activating the DRAM or the like. In the conventional method, a test circuit is prepared in which the contact check can be carried out by accurately setting the timing of associated signals. This method, however, unavoidably leads to the disadvantage of a relatively high cost for the contact check.
To cope with this disadvantage, a logic device such as a gate array is fabricated so as to include a simple test circuit therein for carrying out the contact check of the terminals by means of a boundary scan method which is usually practiced in the field of semiconductor device industry. The test circuit of this type requires no complicated setting of the timing of associated signals, and therefore the contact check of the terminals of the logic device can be easily carried out.
When carrying out the contact check with the above boundary scan method, or the like, described above, however, at least one additional terminal is usually required for activating the test circuit for contact check. In general, the logic device has many terminals (200 to 256 pins, for example) and is fabricated as a custom-made product based on a user""s specification, and therefore at least one dedicated terminal can be easily provided for activating the test circuit for contact check.
However, in the case in which the test circuit for contact check of the logic device described above is to be applied to a memory device such as a DRAM, the following problems occur when activating the test circuit.
The memory device is often fabricated as a general-purpose product and usually designed with the minimum required number of terminals. For the memory device such as the DRAM, therefore it is difficult to provide any additional terminal that may be dedicated to the test circuit.
Further, in view of the need for carrying out the test for contact check with the memory device being mounted on the board, it is difficult to activate the test circuit by applying a specific voltage to a specific terminal.
In carrying out the contact check of the terminals of a semiconductor device consisting of a memory device such as a DRAM, therefore, a test circuit is required which can be activated by setting the timing of associated signals simply within the voltage range normally applied and also by utilizing existing terminals. On the other hand, such a test circuit must not be easily activated in the conditions of normal operations of the memory device, other than the conditions of the test for the terminal contact check, in order to prevent the test circuit from having an influence on the normal operations of the memory device.
The present invention has been developed in view of the above-mentioned problems, and the object thereof is to provide a semiconductor device including a test circuit which can be activated with a simple activation sequence without any dedicated terminal and, which is not easily activated in the condition of normal operations, a method of testing the terminals by utilizing the above test circuit or the like, and a semiconductor integrated circuit having the above test circuit.
In order to solve the problems mentioned above, according to the present invention, there is provided a semiconductor device comprising a terminal test circuit for testing the state of the contact of an external terminal; and a test mode control circuit unit for outputting a signal indicating a first operation mode when a power supply voltage is applied thereto, for outputting a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal in the first operation mode, and for outputting a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes.
According to another aspect of the present invention, there is provided a method of testing the terminals of a semiconductor device, comprising the steps of:
carrying out a first test by applying a power supply voltage to the power supply terminal of the semiconductor device and supplying a chip select signal of an active level to a chip select terminal in the semiconductor device thereby to check the state of the contact of the chip select terminal and the power supply terminal;
carrying out a second test by returning the chip select signal to an inactive level and then restoring the chip select signal to an active level, and activating a test circuit for checking the state of the contact any input terminals other than the chip select terminal thereby to check the state of the contact of the input terminals; and
carrying out a third test by returning the chip select signal to an inactive level and then restoring the chip select signal to an active level, and activating the test circuit for checking the state of the contact of at least a data input/output terminal thereby to check the state of the contact of the data input/output terminal.
According to still another aspect of the present invention, there is provided a semiconductor integrated circuit comprising a first external terminal and a second external terminal each connected to an internal circuit; a test mode control circuit unit which is activated when a power supply voltage is applied thereto to output a test mode signal in response to a control signal applied to the first external terminal, and is deactivated when the logic level of the control signal changes the number of times equal to a predetermined value; and a terminal test circuit unit connected to the second external terminal to determine the state of the contact of the second external terminal in response to the test mode signal.
More specifically, in the semiconductor device and the testing method according to the present invention, the test circuit is activated asynchronously with a clock by switching on power and supplying the chip select signal to a specific terminal such as a chip select terminal, and the test circuit is automatically deactivated after supplying the chip select signal a predetermined number of times.
The test circuit is controlled by the chip select signal from the chip select terminal for the reason mentioned below.
Specifically, the chip select signal has the function of selecting only one memory device among a plurality of memory devices sharing a data bus on the board packaged with a plurality of the memory devices. By designing the semiconductor device so as to select one of the memory devices by means of the chip select signal and output the test result to the data bus from the data output terminal of the selected memory device, therefore, a test can be carried out independently for each memory device.
More specifically, the test is carried out on the memory devices mounted on the board in accordance with the following sequence (1) to (4).
(1) Upon application of a power supply voltage, a starter signal or the like is generated in a memory device whereby the memory device assumes the test mode.
(2) The chip select terminal in the memory device is set to a first level (xe2x80x9cHxe2x80x9d (high) level, for example) so that the memory device enters a non-select state.
(3) When the chip select terminal is set to a second level (xe2x80x9cLxe2x80x9d (low) level, for example) by being supplied with the chip select signal, the test circuit in the memory device is activated and the test is carried out.
(4) When the chip select terminal is set to the first level again, the test circuit is deactivated into a normal operation mode, and hereinafter, the test mode is not assumed.
In this case, the memory device has mounted thereon such a test circuit that the normal operation mode is assumed when detecting twice the fact that the test mode is assumed by the application of a power supply voltage and the chip select terminal is set to the first level.
In the case in which the terminals of the memory device are tested in a plurality of groups, on the other hand, the test is carried out in accordance with the following sequence (1) to (8). In this case, it is supposed that the test is carried out on three groups of terminals including the terminals of a first group (the chip select terminal and the power supply terminal), the terminals of a second group (any input terminals other than the chip select terminal) and the terminals of a third group (the data input/output terminal).
(1) Upon application of a power supply voltage, a starter signal or the like is generated so that the memory device assumes the test mode.
(2) The chip select terminal is set to the first level (xe2x80x9cHxe2x80x9d level, for example) so that the memory device enters a non-select state.
(3) when the chip select signal is supplied to the chip select terminal so that the chip select terminal is set to the second level (xe2x80x9cLxe2x80x9d level, for example), the test circuit is activated to carry out the test on the terminals of the first group.
(4) When the chip select terminal is set to the first level (xe2x80x9cHxe2x80x9d level, for example), the test circuit is deactivated.
(5) When the chip select terminal is set to the second level (xe2x80x9cLxe2x80x9d level, for example) again, the test circuit is activated and the terminals of the second group are tested.
(6) When the chip select terminal is set to the first level (xe2x80x9cHxe2x80x9d level, for example), the test circuit is deactivated.
(7) When the chip select signal is set to the second level (xe2x80x9cLxe2x80x9d level, for example) again, the test circuit is activated and the test is carried out on the terminals of the third group.
(8) When the chip select terminal is set to the first level (xe2x80x9cHxe2x80x9d level, for example), the test circuit is deactivated into a normal operation mode and hereinafter, the test mode is not assumed.
In this case, the memory device has mounted thereon such a test circuit that the normal operation mode is assumed when it is detected, four times, that the test mode is assumed by the application of a power supply voltage and the chip select terminal is set to the first level.
In the case in which a contact check is desired for the terminals of a personal computer or the like, a test for checking the state of the contact of a plurality of groups of terminals is carried out in accordance with the sequence described above.
In normal operations, on the other hand, once a signal of predetermined level is input to the chip select terminal a predetermined number of times and the normal operation mode is assumed after activating the personal computer or the like, the test mode is not erroneously assumed subsequently.
As described above, according to the present invention, the test circuit is activated with a simple activation sequence within a normally applied voltage range by using the existing terminals such as the chip select terminal, and at the same time the test circuit is not easily activated in the condition of normal operations. Therefore, the test such as the contact check of the terminals can be carried out by a method simpler than in the prior art without affecting the condition of normal operations.